REW=0, DREQE=0, BIGEND=0, DCLRM=0, RCNT=0, MBW=00, CURPIPE=others
D1FIFO Port Select Register
| CURPIPE | FIFO Port Access Pipe Specification 0 (0000): No pipe specified 0 (others): Setting prohibited 1 (0001): Pipe 1 2 (0010): Pipe 2 3 (0011): Pipe 3 4 (0100): Pipe 4 5 (0101): Pipe 5 6 (0110): Pipe 6 7 (0111): Pipe 7 8 (1000): Pipe 8 9 (1001): Pipe 9 |
| BIGEND | FIFO Port Endian Control 0 (0): Little endian 1 (1): Big endian |
| MBW | FIFO Port Access Bit Width 0 (00): 8-bit width 1 (01): 16-bit width 2 (10): 32-bit width 3 (11): Setting prohibited |
| DREQE | UCL_Dx_DREQ Signal Output Enable 0 (0): Disables the output 1 (1): Enables the output |
| DCLRM | Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read 0 (0): Auto buffer clear mode is disabled 1 (1): Auto buffer clear mode is enabled |
| REW | Buffer Pointer Rewind 0 (0): The buffer pointer is not rewound 1 (1): The buffer pointer is rewound |
| RCNT | Read Count Mode 0 (0): The DTLN bits are cleared when all of the receive data has been read from the CFIFO 1 (1): The DTLN bits are decremented each time the receive data is read from the CFIFO |